VHDL Code For 3x8 Decoder

The following is the VHDL code for 3x8 decoder in behavioral style along with the test bench.

• SOURCE CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity deco1 is

   Port ( x : in  STD_LOGIC;

          y : in  STD_LOGIC;

          z : in  STD_LOGIC;

          d0 : out  STD_LOGIC;

          d1 : out  STD_LOGIC;

          d2 : out  STD_LOGIC;

          d3 : out  STD_LOGIC;

          d4 : out  STD_LOGIC;

          d5 : out  STD_LOGIC;

          d6 : out  STD_LOGIC;

          d7 : out  STD_LOGIC);

end deco1;

architecture Structural of deco1 is

component decand1 is

Port ( a : in  STD_LOGIC;

          b : in  STD_LOGIC;

          c : in  STD_LOGIC;

          d : out  STD_LOGIC);

end component;

component decnot1 is

Port ( a : in  STD_LOGIC;

          c : out  STD_LOGIC);

end component;

signal s2, s1, s3: STD_LOGIC;

begin

g1: decnot1 port map(x,s1);

g2: decnot1 port map(y,s2);

g3: decnot1 port map(z,s3);

g4: decand1 port map(s1, s2, s3, d0);

g5: decand1 port map(s1, s2, z, d1);

g6: decand1 port map(s1, y, s3, d2);

g7: decand1 port map(s1, y, z, d3);

g8: decand1 port map(x, s2, s3, d4);

g9: decand1 port map(x, s2, z, d5);

g10: decand1 port map(x, y, s3, d6);

g11: decand1 port map(x, y, z, d7);

end Structural;

• TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY deco2_tb IS

END deco2_tb;

ARCHITECTURE behavior OF deco2_tb IS

   -- Component Declaration for the Unit Under Test (UUT)

   COMPONENT deco1

   PORT(

        x : IN  std_logic;

        y : IN  std_logic;

        z : IN  std_logic;

        d0 : OUT  std_logic;

        d1 : OUT  std_logic;

        d2 : OUT  std_logic;

        d3 : OUT  std_logic;

        d4 : OUT  std_logic;

        d5 : OUT  std_logic;

        d6 : OUT  std_logic;

        d7 : OUT  std_logic

       );

   END COMPONENT;

  

  --Inputs

  signal x : std_logic := '0';

  signal y : std_logic := '0';

  signal z : std_logic := '0';

    --Outputs

  signal d0 : std_logic;

  signal d1 : std_logic;

  signal d2 : std_logic;

  signal d3 : std_logic;

  signal d4 : std_logic;

  signal d5 : std_logic;

  signal d6 : std_logic;

  signal d7 : std_logic;

BEGIN

    -- Instantiate the Unit Under Test (UUT)

  uut: deco1 PORT MAP (

         x => x,

         y => y,

         z => z,

         d0 => d0,

         d1 => d1,

         d2 => d2,

         d3 => d3,

         d4 => d4,

         d5 => d5,

         d6 => d6,

         d7 => d7

       );

  -- Stimulus process

  stim_proc: process

  begin       

     x<='0'; y<='0';z<='0';

        wait for 100ns;

        x<='0'; y<='0';z<='1';

        wait for 100ns;

        x<='0'; y<='1';z<='0';

        wait for 100ns;

        x<='0'; y<='1';z<='1'; wait for 100ns;

        x<='1'; y<='0';z<='0';wait for 100ns;

        x<='1'; y<='0';z<='1';wait for 100ns;

        x<='1'; y<='1';z<='0';wait for 100ns;

        x<='1'; y<='1';z<='1';wait for 100ns;

  end process;

END;

Test Bench Waveform: