VHDL Code For Sequence Detector

VHDL Code for the sequence 1010(overlapping allowed) is given below:

State Diagram:

(Image Source: Google)

• Source Code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--Sequence detector for detecting the sequence "1011".
--Non overlapping type.
entity seq_det is
port(   clk : in std_logic;
        reset : in std_logic;
        input : in std_logic;    --input bit sequence   
        output : out std_logic  --'1' indicates the pattern "1010" is detected in the sequence.
        );
end seq_det;

architecture Behavioral of seq_det is

type state_type is (s0,s1,s2,s3);  --Defines the type for states in the state machine
signal state : state_type := s0;  --Declare the signal with the corresponding state type.

begin

process(clk, reset)
begin
    if( reset = '1' ) then     --resets state and output signal when reset is asserted.
        output <= '0';
        state <= s0;
    elsif ( clk' event and clk='1' ) then   --at rising edge of clock
        case state is
            when s0 =>   --when the current state is s0
                output <= '0';
                if ( input = '0' ) then
                    state <= s0;
                else   
                    state <= s1;
                end if;
            when s1 =>   --when the current state is s1
                if ( input = '0' ) then
                    state <= s2;
      output<='0';
                else   
                    state <= s1;
     output<='0';
                end if;
            when s2 =>   --when the current state is s2
                if ( input = '0' ) then
                    state <= s0;
output<='0';
                else   
                    state <= s3;
output<='0';
                end if;
            when s3 =>   --when the current state is s3
output<='1';
                if ( input = '0' ) then
                    state <= s1;
                else   
                    state <= s2;
                    output <= '1';   --Output is 1 when the pattern "1010" is found in the sequence.
                end if;    
            when others =>
                NULL;
        end case;
    end if;
end process;   

end Behavioral;

• Test Bench

The sequence 0101011010 is given as input.

ENTITY seqdetect_tb IS
END seqdetect_tb;

ARCHITECTURE behavior OF seqdetect_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT seq_det
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         input : IN  std_logic;
         output : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal input : std_logic := '0';

  --Outputs
   signal output : std_logic;

   -- Clock period definitions
   constant clk_period : time := 100 ns;

BEGIN

 -- Instantiate the Unit Under Test (UUT)
   uut: seq_det PORT MAP (
          clk => clk,
          reset => reset,
          input => input,
          output => output
        );

   -- Clock process definitions
   clk_process :process
   begin
  clk <= '0';
  wait for clk_period/2;
  clk <= '1';
  wait for clk_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
     input<='0';
   wait for 100 ns;
input<='1';
   wait for 100 ns;
   input<='0';
   wait for 100 ns;
   input<='1';
   wait for 100 ns;
   input<='0';
   wait for 100 ns;
   input<='1';
   wait for 100 ns;
   input<='1';
   wait for 100 ns;
input<='0';
   wait for 100 ns;
input<='1';
   wait for 100 ns;
input<='0';
   wait for 100 ns;   
  
     -- wait for clk_period*10;

      -- insert stimulus here

     -- wait;
   end process;

END;

Waveform:

VHDL CODE FOR D FLIP FLOP

The following is the VHDL code for D flip flop:

• Source Code

entity dff1 is

   Port ( d : in  STD_LOGIC;

           reset : in  STD_LOGIC;

             CLOCK: in STD_LOGIC;

          q : out  STD_LOGIC

          );

end dff1;

architecture Behavioral of dff1 is

begin

process(CLOCK)

begin

if ((CLOCK = '1') and CLOCK'EVENT) then

Q <= D after 5 ns;

end if;

end process;

end Behavioral;

• Test Bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY dff_tb IS

END dff_tb;

ARCHITECTURE behavior OF dff_tb IS

   -- Component Declaration for the Unit Under Test (UUT)

   COMPONENT dff1

   PORT(

        d : IN  std_logic;

        reset : IN  std_logic;

        CLOCK : IN  std_logic;

        q : OUT  std_logic

       );

   END COMPONENT;

  --Inputs

  signal d : std_logic := '0';

  signal reset : std_logic := '0';

  signal CLOCK : std_logic := '0';

    --Outputs

  signal q : std_logic;

  -- Clock period definitions

 -- constant CLOCK_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)

  uut: dff1 PORT MAP (

         d => d,

         reset => reset,

         CLOCK => CLOCK,

         q => q

       );

  -- Clock process definitions

  CLOCK_process :process

  begin

        CLOCK <= '0';

        wait for 50ns;

        CLOCK <= '1';

        wait for 50ns;

  end process;

  -- Stimulus process

  stim_proc: process

  begin       

     d<='1';

        wait for 100ns;

        d<='0';

        wait for 100ns;

  end process;

END;

Output: