Monday, 19 December 2016

VHDL Code For Full Adder Using Components

The code for full adder using structural modelling is given below along with the source codes for various components used in the code for the full adder.

--Code for xor gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor1 is
    Port ( a : in  bit;
           b : in  bit;
           c : out  bit);
end xor1;
architecture Behavioral of xor1 is
begin
c <= a xor b;
end Behavioral; 
---------------------------------------------------------------------------------------------------------------------------
--Code for and gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and1 is
    Port ( a : in  bit;
           b : in  bit;
           c : out  bit);
end and1;
architecture Behavioral of and1 is
begin
c<= a and b;
end Behavioral;
---------------------------------------------------------------------------------------------------------------------------
--Code for or gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or1 is
    Port ( a : in  bit;
           b : in  bit;
           c : out  bit);
end or1;
architecture Behavioral of or1 is
begin
c<= a or b;
end Behavioral;
---------------------------------------------------------------------------------------------------------------------------
Code for full adder using the above components.
  • SOURCE CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladd is
    Port ( x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           sum : out  STD_LOGIC;
           cout : out  STD_LOGIC);
end fulladd;

architecture Structural of fulladd is
component or1 is
Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end component;

component xor1 is
Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end component;

component and1 is
Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end component;

signal s1, s2, s3:STD_LOGIC;

begin

g1:xor1 port map(x,y,s1);
g2:xor1 port map(s1, cin, sum);
g3:and1 port map(x, y, s2);
g4:and1 port map(s1, cin, s3);
g5:or1 port map(s2, s3, cout);

end Structural;
  • TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 ENTITY full1_tb IS
END full1_tb;

ARCHITECTURE behavior OF full1_tb IS
    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT fulladd

    PORT(
         x : IN  STD_LOGIC;
         y : IN  STD_LOGIC;
         cin : IN  STD_LOGIC;
         sum : OUT  STD_LOGIC;
         cout : OUT  STD_LOGIC
        );

    END COMPONENT;
   --Inputs
   signal x : STD_LOGIC := '0';
   signal y : STD_LOGIC := '0';
   signal cin : STD_LOGIC := '0';

                --Outputs
   signal sum : STD_LOGIC;
   signal cout : STD_LOGIC;

BEGIN
                -- Instantiate the Unit Under Test (UUT)

   uut: fulladd PORT MAP (
          x => x,
          y => y,
          cin => cin,
          sum => sum,
          cout => cout
        );

   -- Stimulus process
   stim_proc: process

   begin                
               x<='0'; y<='0' ; cin<='0'; wait for 100 ns;
               x<='0'; y<='0' ; cin<='1'; wait for 100 ns;
               x<='0'; y<='1' ; cin<='0'; wait for 100 ns;
               x<='0'; y<='0' ; cin<='1'; wait for 100 ns;         
               x<='1'; y<='0' ; cin<='0'; wait for 100 ns;         
               x<='1'; y<='0' ; cin<='1'; wait for 100 ns;         
               x<='1'; y<='1' ; cin<='0'; wait for 100 ns;
               x<='1'; y<='1' ; cin<='1'; wait for 100 ns;                                         
   end process;
END;

 Waveform:
Full Adder in structural modelling

RTL Schematic:
Full Adder RTL Schematic


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Sunday, 18 December 2016

VHDL Code For Full Adder

The following is the code for full adder in behavioral style.
  • SOURCE CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity add1 is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           sum : out  STD_LOGIC;
           cout : out  STD_LOGIC);
end add1;

architecture Behavioral of add1 is

begin
sum<= a xor b xor cin;
cout<= (a and b) or (cin and (a xor b));
end Behavioral;
  •     TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 ENTITY add2_tb IS
END add2_tb;

 ARCHITECTURE behavior OF add2_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

     COMPONENT add1

    PORT(

         a : IN  STD_LOGIC;

         b : IN  STD_LOGIC;

         cin : IN  STD_LOGIC;

         sum : OUT  STD_LOGIC;

         cout : OUT  STD_LOGIC

        );

    END COMPONENT;

   --Inputs

   signal a : STD_LOGIC := '0';
   signal b : STD_LOGIC := '0';
   signal cin : STD_LOGIC := '0';

                 --Outputs
   signal sum : STD_LOGIC;
   signal cout : STD_LOGIC;

BEGIN
                -- Instantiate the Unit Under Test (UUT)

   uut: add1 PORT MAP (
          a => a,
          b => b,
          cin => cin,
          sum => sum,
          cout => cout
        );

   -- Stimulus process

   stim_proc: process

   begin                

      a <= '0'; b <= '0'; cin <= '0';
      wait for 100 ns;

      a <= '0'; b <= '0'; cin <= '1';
      wait for 100 ns;

      a <= '0'; b <= '1'; cin <= '0';
      wait for 100 ns;

      a <= '0'; b <= '1'; cin <= '1';
      wait for 100 ns;

      a <= '1'; b <= '0'; cin <= '0';
      wait for 100 ns;

      a <= '1'; b <= '0'; cin <= '1';
      wait for 100 ns;  

      a <= '1'; b <= '1'; cin <= '0';
      wait for 100 ns;

      a <= '1'; b <= '1'; cin <= '1';
      wait for 100 ns;
   end process;

END;

Waveform:
Waveform of Full Adder



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Friday, 16 December 2016

VHDL Code For Half Adder

The following is the VHDL code for the implementation of Half Adder using Behavioral modelling.
  •   SOURCE CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity halfa is

    Port ( x : in  STD_LOGIC;

           y : in  STD_LOGIC;

           sum : out  STD_LOGIC;

           cout : out  STD_LOGIC);
end halfa;

architecture Behavioral of halfa is

begin
sum<= x xor y;
cout<= x and y;

end Behavioral;
  • TESTBENCH


 LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY h1_tb IS

END h1_tb;

ARCHITECTURE behavior OF h1_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT halfa

    PORT(

         x : IN  STD_LOGIC;

         y : IN  STD_LOGIC;

         sum : OUT  STD_LOGIC;

         cout : OUT  STD_LOGIC

        );

    END COMPONENT;

   --Inputs

   signal x : STD_LOGIC := '0';

   signal y : STD_LOGIC := '0';

                --Outputs

   signal sum : STD_LOGIC;

   signal cout : STD_LOGIC;

BEGIN
                -- Instantiate the Unit Under Test (UUT)

   uut: halfa PORT MAP (

          x => x,

          y => y,

          sum => sum,

          cout => cout

        );

   -- Stimulus process

   stim_proc: process

   begin                
                               x<='0'; y<='0';
      wait for 100 ns;         
                                x<='0'; y<='1';
      wait for 100 ns;         
                                x<='1'; y<='0';
      wait for 100 ns;         
                                x<='1'; y<='1';
      wait for 100 ns;         

   end process;
END;

 Waveform:
Half Adder Using Behavioral Modelling

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Thursday, 15 December 2016

VHDL Codes For Logical Gates

The following are the codes for some of the logical gates  along with the test bench in behavioral style.

1. AND GATE
  • SOURCE CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity a1 is
    Port ( i1 : in  std_logic;
           i2 : in  std_logic;
           o : out  std_logic);
end a1;
architecture Behavioral of a1 is
begin
o<= i1 and i2;
end Behavioral;
  • TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY aa_tb IS
END aa_tb;

ARCHITECTURE behavior OF aa_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT aa
    PORT(
         i1 : std_logic  ;
         i2 : std_logic  ;
         o : std_logic
        );
    END COMPONENT;
   
   --Inputs
   signal i1 : std_logic := '0';
   signal i2 : std_logic := '0';
  --Outputs
   signal o : std_logic;

BEGIN

 -- Instantiate the Unit Under Test (UUT)
   uut: aa PORT MAP (
          i1 => i1,
          i2 => i2,
          o => o
        );
   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
     i1<='0'; i2<='0';
      wait for 100 ns;
  i1<='0'; i2<='1';
      wait for 100 ns;
  i1<='1'; i2<='0';
      wait for 100 ns;
  i1<='1'; i2<='1';
      wait for 100 ns; 
   end process;
END;

Waveform:
And Gate Test Bench


2. XOR GATE
  • SOURCE CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xx is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end xx;
architecture Behavioral of xx is
begin
c<= a xor b;
end Behavioral;
  • TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY xox IS
END xox;
ARCHITECTURE behavior OF xox IS
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT xx
    PORT(
         a : IN  STD_LOGIC;
         b : IN  STD_LOGIC;
         c : OUT  STD_LOGIC
        );
    END COMPONENT;
   --Inputs
   signal a : STD_LOGIC := '0';
   signal b : STD_LOGIC := '0';

                --Outputs
   signal c : STD_LOGIC;
BEGIN
                -- Instantiate the Unit Under Test (UUT)
   uut: xx PORT MAP (
          a => a,
          b => b,
          c => c
        );
   -- Stimulus process
   stim_proc: process
   begin                
a<='0'; b<='0';
      wait for 100 ns;         
a<='0'; b<='1';
      wait for 100 ns;         
                                a<='1'; b<='0';
      wait for 100 ns;         
                                a<='1'; b<='1';
      wait for 100 ns;         
   end process;

END;

Waveform:
Xor gate test bench

3. NOR GATE
  • SOURCE CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity n1 is
    Port ( x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           z : out STD_LOGIC);
end n1;
architecture Behavioral of n1 is
begin
z<= x nor y;
end Behavioral;
  •  TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY nn IS
END nn;
ARCHITECTURE behavior OF nn IS
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT n1
    PORT(
         x : IN  STD_LOGIC;
         y : IN  STD_LOGIC;
         z : OUT  STD_LOGIC
        );
    END COMPONENT;
 
   --Inputs
   signal x : STD_LOGIC := '0';
   signal y : STD_LOGIC := '0';

                --Outputs
   signal z : STD_LOGIC;
BEGIN
                -- Instantiate the Unit Under Test (UUT)
   uut: n1 PORT MAP (
          x => x,
          y => y,
          z => z
        );
   -- Stimulus process
   stim_proc: process
   begin                
      x<='0'; y<='0'; wait for 100 ns;
      x<='0'; y<='1'; wait for 100 ns;
       x<='1'; y<='0'; wait for 100 ns;
       x<='1'; y<='1'; wait for 100 ns                             
   end process;
END;

Waveform:
Nor gate test bench


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