VHDL Code For Full Adder

The following is the code for full adder in behavioral style.

• SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity add1 is

    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           sum : out  STD_LOGIC;
           cout : out  STD_LOGIC);
end add1;

architecture Behavioral of add1 is

begin

sum<= a xor b xor cin;
cout<= (a and b) or (cin and (a xor b));
end Behavioral;

•     TEST BENCH

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 ENTITY add2_tb IS
END add2_tb;

 ARCHITECTURE behavior OF add2_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

     COMPONENT add1

    PORT(

         a : IN  STD_LOGIC;

         b : IN  STD_LOGIC;

         cin : IN  STD_LOGIC;

         sum : OUT  STD_LOGIC;

         cout : OUT  STD_LOGIC

        );

    END COMPONENT;

   --Inputs

   signal a : STD_LOGIC := '0';

   signal b : STD_LOGIC := '0';
   signal cin : STD_LOGIC := '0';

                --Outputs
   signal sum : STD_LOGIC;
   signal cout : STD_LOGIC;

BEGIN

                -- Instantiate the Unit Under Test (UUT)

   uut: add1 PORT MAP (

          a => a,
          b => b,
          cin => cin,
          sum => sum,
          cout => cout
        );

   -- Stimulus process

   stim_proc: process

   begin                

      a <= '0'; b <= '0'; cin <= '0';

      wait for 100 ns;

      a <= '0'; b <= '0'; cin <= '1';

      wait for 100 ns;

      a <= '0'; b <= '1'; cin <= '0';

      wait for 100 ns;

      a <= '0'; b <= '1'; cin <= '1';

      wait for 100 ns;

      a <= '1'; b <= '0'; cin <= '0';

      wait for 100 ns;

      a <= '1'; b <= '0'; cin <= '1';

      wait for 100 ns;  

      a <= '1'; b <= '1'; cin <= '0';

      wait for 100 ns;

      a <= '1'; b <= '1'; cin <= '1';

      wait for 100 ns;
   end process;

END;

Waveform: