VHDL Code For Half Subtractor

The following is the code for half adder in structural modelling. The source codes for various components are also given:

• SOURCE CODE

--Not Gate

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

component notg is

Port ( a : in  STD_LOGIC;

c : out  STD_LOGIC);

end component;

architecture Structural of xorg is

begin

c<= not a;

end structural;

--------------------------------------------------------------------------------------------------------------------------

--And Gate

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

Port ( a : in  STD_LOGIC;

b : in  STD_LOGIC;

c : out  STD_LOGIC);

end component;

architecture Structural of xorg is

begin

c<= a and b;

end structural;

--------------------------------------------------------------------------------------------------------------------------

--Xor Gate

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity xor is

   component xorg is

Port ( a : in  STD_LOGIC;

b : in  STD_LOGIC;

c : out  STD_LOGIC);

end component;

architecture Structural of xorg is

begin

c<= a xor b;

end structural;

--------------------------------------------------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity sub2 is

    Port ( x : in  STD_LOGIC;

y : in  STD_LOGIC;

dif : out  STD_LOGIC;

bor : out  STD_LOGIC);

end sub2;

architecture Structural of sub2 is

component xorg is

Port ( a : in  STD_LOGIC;

b : in  STD_LOGIC;

c : out  STD_LOGIC);

end component;

component andg is

Port ( a : in  STD_LOGIC;

b : in  STD_LOGIC;

c : out  STD_LOGIC);

end component;

component notg is

Port ( a : in  STD_LOGIC;

c : out  STD_LOGIC);

end component;

signal s1:STD_LOGIC;

begin

g1: xorg port map(x, y, dif);

g2: notg port map(x, s1);

g3: andg port map(s1, y, bor);

end Structural;

•  TESTBENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY sub1_tb IS

END sub1_tb;

ARCHITECTURE behavior OF sub1_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT sub2

PORT(

x : IN  STD_LOGIC;

y : IN  STD_LOGIC;

dif : OUT  STD_LOGIC;

bor : OUT  STD_LOGIC

        );

    END COMPONENT;

   --Inputs

   signal x :STD_LOGIC := '0';

   signal y :STD_LOGIC := '0';

               --Outputs

   signal dif :STD_LOGIC;

   signal bor :STD_LOGIC;

BEGIN

               -- Instantiate the Unit Under Test (UUT)

uut: sub2 PORT MAP (

          x => x,

          y => y,

dif =>dif,

bor =>bor

        );

   -- Stimulus process

stim_proc: process

   begin                

      x<='0'; y<='0';

      wait for 100 ns;          

                              x<='0'; y<='1';

      wait for 100 ns;          

                              x<='1'; y<='0';

      wait for 100 ns;          

                              x<='1'; y<='1';

      wait for 100 ns;          

       end process;

END;

Waveform: