VHDL CODE FOR D FLIP FLOP

The following is the VHDL code for D flip flop:

• Source Code

entity dff1 is

   Port ( d : in  STD_LOGIC;

           reset : in  STD_LOGIC;

             CLOCK: in STD_LOGIC;

          q : out  STD_LOGIC

          );

end dff1;

architecture Behavioral of dff1 is

begin

process(CLOCK)

begin

if ((CLOCK = '1') and CLOCK'EVENT) then

Q <= D after 5 ns;

end if;

end process;

end Behavioral;

• Test Bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY dff_tb IS

END dff_tb;

ARCHITECTURE behavior OF dff_tb IS

   -- Component Declaration for the Unit Under Test (UUT)

   COMPONENT dff1

   PORT(

        d : IN  std_logic;

        reset : IN  std_logic;

        CLOCK : IN  std_logic;

        q : OUT  std_logic

       );

   END COMPONENT;

  --Inputs

  signal d : std_logic := '0';

  signal reset : std_logic := '0';

  signal CLOCK : std_logic := '0';

    --Outputs

  signal q : std_logic;

  -- Clock period definitions

 -- constant CLOCK_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)

  uut: dff1 PORT MAP (

         d => d,

         reset => reset,

         CLOCK => CLOCK,

         q => q

       );

  -- Clock process definitions

  CLOCK_process :process

  begin

        CLOCK <= '0';

        wait for 50ns;

        CLOCK <= '1';

        wait for 50ns;

  end process;

  -- Stimulus process

  stim_proc: process

  begin       

     d<='1';

        wait for 100ns;

        d<='0';

        wait for 100ns;

  end process;

END;

Output:

VHDL Code For Half Adder

The following is the VHDL code for the implementation of Half Adder using Behavioral modelling.

•   SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity halfa is

    Port ( x : in  STD_LOGIC;

           y : in  STD_LOGIC;

           sum : out  STD_LOGIC;

           cout : out  STD_LOGIC);

end halfa;

architecture Behavioral of halfa is

begin

sum<= x xor y;

cout<= x and y;

end Behavioral;

• TESTBENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY h1_tb IS

END h1_tb;

ARCHITECTURE behavior OF h1_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT halfa

    PORT(

         x : IN  STD_LOGIC;

         y : IN  STD_LOGIC;

         sum : OUT  STD_LOGIC;

         cout : OUT  STD_LOGIC

        );

    END COMPONENT;

   --Inputs

   signal x : STD_LOGIC := '0';

   signal y : STD_LOGIC := '0';

                --Outputs

   signal sum : STD_LOGIC;

   signal cout : STD_LOGIC;

BEGIN

                -- Instantiate the Unit Under Test (UUT)

   uut: halfa PORT MAP (

          x => x,

          y => y,

          sum => sum,

          cout => cout

        );

   -- Stimulus process

   stim_proc: process

   begin                

                               x<='0'; y<='0';
      wait for 100 ns;         
                                x<='0'; y<='1';
      wait for 100 ns;         
                                x<='1'; y<='0';
      wait for 100 ns;         
                                x<='1'; y<='1';
      wait for 100 ns;         

   end process;

END;

Waveform:

VHDL Codes For Logical Gates

The following are the codes for some of the logical gates  along with the test bench in behavioral style.

1. AND GATE

• SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity a1 is
    Port ( i1 : in  std_logic;
           i2 : in  std_logic;
           o : out  std_logic);
end a1;

architecture Behavioral of a1 is

begin
o<= i1 and i2;

end Behavioral;

• TEST BENCH

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY aa_tb IS
END aa_tb;

ARCHITECTURE behavior OF aa_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT aa
    PORT(
         i1 : std_logic  ;
         i2 : std_logic  ;
         o : std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal i1 : std_logic := '0';
   signal i2 : std_logic := '0';

  --Outputs
   signal o : std_logic;

BEGIN

 -- Instantiate the Unit Under Test (UUT)
   uut: aa PORT MAP (
          i1 => i1,
          i2 => i2,
          o => o
        );

   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
     i1<='0'; i2<='0';
      wait for 100 ns;
  i1<='0'; i2<='1';
      wait for 100 ns;
  i1<='1'; i2<='0';
      wait for 100 ns;
  i1<='1'; i2<='1';
      wait for 100 ns; 

   end process;

END;

Waveform:

2. XOR GATE

• SOURCE CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity xx is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           c : out  STD_LOGIC);

end xx;

architecture Behavioral of xx is

begin

c<= a xor b;

end Behavioral;

• TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY xox IS

END xox;

ARCHITECTURE behavior OF xox IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT xx

    PORT(

         a : IN  STD_LOGIC;

         b : IN  STD_LOGIC;

         c : OUT  STD_LOGIC

        );

    END COMPONENT;

   --Inputs

   signal a : STD_LOGIC := '0';

   signal b : STD_LOGIC := '0';

                --Outputs

   signal c : STD_LOGIC;

BEGIN

                -- Instantiate the Unit Under Test (UUT)

   uut: xx PORT MAP (

          a => a,

          b => b,

          c => c

        );

   -- Stimulus process

   stim_proc: process

   begin                

a<='0'; b<='0';

      wait for 100 ns;         

a<='0'; b<='1';

      wait for 100 ns;         

                                a<='1'; b<='0';

      wait for 100 ns;         

                                a<='1'; b<='1';

      wait for 100 ns;         

   end process;

END;

Waveform:

3. NOR GATE

• SOURCE CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity n1 is

    Port ( x : in  STD_LOGIC;

           y : in  STD_LOGIC;

           z : out STD_LOGIC);

end n1;

architecture Behavioral of n1 is

begin

z<= x nor y;

end Behavioral;

•  TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY nn IS

END nn;

ARCHITECTURE behavior OF nn IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT n1

    PORT(

         x : IN  STD_LOGIC;

         y : IN  STD_LOGIC;

         z : OUT  STD_LOGIC

        );

    END COMPONENT;

 

   --Inputs

   signal x : STD_LOGIC := '0';

   signal y : STD_LOGIC := '0';

                --Outputs

   signal z : STD_LOGIC;

BEGIN

                -- Instantiate the Unit Under Test (UUT)

   uut: n1 PORT MAP (

          x => x,

          y => y,

          z => z

        );

   -- Stimulus process

   stim_proc: process

   begin                

      x<='0'; y<='0'; wait for 100 ns;

      x<='0'; y<='1'; wait for 100 ns;

       x<='1'; y<='0'; wait for 100 ns;

       x<='1'; y<='1'; wait for 100 ns                             

   end process;

END;

Waveform: